1. Field of the Invention
This invention relates to integrated circuit manufacture and more particularly to an insulating layer having adjustable chemical and mechanical properties which can be polish removed at a rate set in accordance with the chosen properties.
2. Description of the Relevant Art
The density of active devices placed upon a single monolithic substrate has steadily increased over the years. As the minimum feature size on an integrated circuit decreases, the active device density increases. As a result, the density of overlying interconnect must also be increased. With limited area, interconnect density is often forced to dimensionally expand above the substrate in a multi-level arrangement. Accordingly, multi-level interconnect structures have become a mainstay in modern integrated circuit manufacture.
In addition to added process complexity, multi-level interconnect causes a loss of topological planarity of the integrated circuit upper surface. Loss of planarity can cause many problems which can impact upon manufacturing yield. Exemplary problems include stringers arising from incomplete etching over severe steps, failure to open vias due to interlevel dielectric thickness disparity, poor adhesion to underlying materials, step coverage problems as well as depth-of-focus problems. Many manufacturers have undergone extensive research in methods for planarizing the topological layers in order to avoid the above problems. Generally speaking, manufacturers have focused upon planarizing the dielectric layers ("interlevel dielectric layers") placed between the levels of multi-level interconnect structures.
A well known method in which to planarize interlevel dielectric layers is through use of a sacrificial etch back technique. Sacrificial etch back involves the use of a conformal dielectric placed over the silicon substrate or lower metalization layer. Next, a planarizing layer, generally a low viscosity liquid which can be cured as a dielectric, is placed over the conformal oxide. The planarizing layer generally comprises either a photoresist, polyimide, or spin-on glass ("SOG"). The planarizing layer is often much thicker than the underlying conformal oxide and is removed at an etch rate substantially similar to the etch rate of the underlying oxide. Oftentimes, the sacrificial planarizing layer is removed in a plasma (typically, O.sub.2 or O.sub.2 mixed with CF.sub.4). The etch process is continued until most, if not all, of the sacrificial planarizing layer is removed leaving a more planar upper surface upon which subsequent interconnect structures can be placed. To achieve the desired degree of planarity and final interlevel dielectric thickness, tight process control is necessary for etch-rate uniformity across the wafer and end-point detection of the etch process.
While a liquid-based planarizing layer has many advantages over CVD deposited or sputter deposited layers, liquid-based layers such as SOG layers generally etch at or near the same etch rate as the underlying conformal oxide layer. By design, many manufacturers fix the etch rate of each layer so that they are substantially similar. Monitoring of etch rate and end-point detection is sometimes difficult under etching methodologies. As a result, more recent planarization schemes utilize chemical-mechanical polishing ("CMP"). CMP has a unique advantage in that it can rapidly remove elevated features without significantly thinning the flat areas. Moreover, CMP can reduce the thickness in raised areas more so than in recessed areas due to the fact that raised areas contact with the polishing pad and are abraded to a greater extent than the recessed areas. By applying mechanical as well as chemical abrasion to the uppermost surfaces, CMP achieves greater planarization than conventional etching (i.e., etching without conjunctive mechanical abrasion).
Recent studies have indicated the importance of fixing detection of a CMP end point. Generally speaking, end-point detection can be fixed by depositing a harder (more dense) material upon a softer (less dense) oxide. An exemplary, CMP etch stop configuration is described in U.S. Pat. No. 5,246,884 to Jaso, et al. In Jaso, et al., a hard CVD diamond-like carbon is placed upon a sputter deposited oxide. The diamond-like carbon is removed at elevated portions. As the elevated portions and underlying oxide are removed to a lower elevational level, the lower elevation diamond-like coated material functions as an etch stop. The lower-coated diamond-like carbon thereby functions to planarize its surface with the removed upper (raised) surface. Diamond-like carbon, like many etch stop substances, cannot be left as part of the interlevel dielectric. Conventional CMP etch stop substances are dissimilar from standard oxides or standard interlevel dielectrics and therefore electrically function differently than the remainder of the interlevel dielectric. Generally speaking, many conventional CMP etch stop materials have chemical and mechanical irregularities which can reduce the dielectric properties of the overall structure.
Another problem often associated with conventional CMP etch stop materials is their inability to take on different chemical and mechanical properties. In many instances, it would be desirable to change the mechanical and chemical properties of the polish etch stop material to match the polish slurry being used or the polish pressure being applied. It would be desirable to fix the chemical and mechanical properties prior to the CMP step so that the etch stop is less susceptible (or possibly more susceptible) to CMP than the underlying conformal insulating material. It would be still further advantageous to be able to vary the chemical and mechanical properties of the CMP etch stop material, in relation to underlying conformal insulating material. For reasons stated above, it would therefore be highly desirable to provide a polish etch stop material above a conformal insulating material, wherein the polish etch stop material takes on a variable chemical and mechanical property fixed prior to CMP.